Semiconductor Device Having Gold Metallization Structures

ABSTRACT

A semiconductor device includes a semiconductor substrate having first and second terminals of one or more semiconductor devices, first and second barrier metal regions electrically connected to the first and second terminals, respectively, and first and second gold metallization structures electrically connected to the first and second terminals via the first and second barrier metal regions, respectively. The first and second gold metallization structures contain diffused copper atoms. Interfaces between the first and second barrier metals and the first and second gold metallization structures, respectively, are substantially devoid of metallic copper.

TECHNICAL FIELD

The present invention generally relates to semiconductor devices andmore particularly relates to techniques for forming gold metallizationlayers that may be connected to one or more semiconductor devices.

BACKGROUND

Metallization layers are commonality utilized in semiconductorapplications for electrically connecting one or more semiconductordevices, such as MOSFETs, IGBTs, diodes, etc. For example, ametallization layer may be used in an integrated circuit to electricallyconnect power and ground potential to individual transistor devices.Further, metallization layers may be used in an integrated circuit asinterconnects for the input and output terminals of the transistors. Avariety of processing techniques are available for forming semiconductormetallization layers such as electroplating, chemical or physical vapordeposition, etc. Lithography techniques are commonly utilized to providemetallization lines with precisely controlled width and pitch

In many cases, copper is a preferred material for semiconductormetallization layers. Copper offers low electrical resistance and istherefore conducive to high frequency switching operation ofsemiconductor devices. Further, copper is advantageous in high powerapplications because it provides low resistive losses and high thermalconductivity. However, copper metal lines may be susceptible toreliability issues. Particularly in the case of high-temperature andhigh-humidity conditions, copper is prone to corrosion, oxidation,and/or electromigration. Unless proper mitigation steps are taken, therisk of electrical short in copper metallization lines (e.g., between asource and drain line) due to copper dendrites and/or cathodic-anodicfilamentation (CAF) may be unacceptably high.

Known techniques for mitigating the risk of electrical short in coppermetallization lines include forming protective layers that seal thecopper and prevent electromigration and/or diffusion of the copper. Forexample, protective layers formed from materials such as nickel (Ni),palladium (Pd) and gold (Au) may be used to protect and seal coppermetallization layers. However, these techniques introduce undesirableexpense and complexity to the process.

SUMMARY

According to an embodiment, a method of forming a metallization forelectrically connecting one or more semiconductor devices is disclosed.According to the method, an electrically conductive barrier layer isformed on a semiconductor substrate such that the barrier layer covers afirst terminal of a device formed in the substrate. A seed layer isformed on the barrier layer. The seed layer extends over the firstterminal and includes a noble metal other than gold. The substrate ismasked with a mask having a first opening that is laterally aligned withthe first terminal such that an unmasked portion of the seed layer isexposed by the first opening and such that a masked portion of the seedlayer is covered by the mask. The unmasked portion of the seed layer iselectroplated using a gold electrolyte solution so as to form a firstgold metallization structure arranged in the first mask opening. Themask is removed and the masked portions of the seed layer and thebarrier layer are removed. The noble metal from the unmasked portion ofthe seed layer is diffused into the first gold metallization structure.The first gold metallization structure is electrically connected to thefirst terminal via the barrier layer.

According to an embodiment, a method of forming a gold metallizationstructure by electrodeposition using a copper seed layer is disclosed.According to the method, an electrically conductive barrier layercovering a surface of a semiconductor substrate is formed. The substrateincludes a source and drain terminal of a semiconductor device. Acontinuous portion of the barrier layer contacts the source and drainterminals. A copper seed layer is formed such that a continuous seedlayer portion covers the continuous portion of the barrier layer. Theseed layer is masked with a mask having first and second openings thatare laterally aligned with the source and drain terminals. Unmaskedportions of the seed layer are electroplated using a gold electrolytesolution so as to form first and second gold metallization structuresarranged in the first and second mask openings. The mask is removed. Themasked portions of the seed layer and the barrier layer are removed soas to electrically isolate the first and second gold metallizationstructures. Copper atoms from the seed layer are diffused into the firstand second gold metallization structures such that respective interfacesbetween the barrier layer and the first and second gold metallizationstructures are substantially devoid of metallic copper. The first andsecond gold metallization structures are electrically connected to thefirst and second terminals, respectively.

According to an embodiment, a semiconductor device is disclosed. Thesemiconductor device includes a substrate having first and secondterminals of one or more semiconductor devices. First and second barriermetal regions are electrically connected to the first and secondterminals, respectively. First and second gold metallization structuresare electrically connected to the first and second terminals via thefirst and second barrier metal regions, respectively. The first andsecond gold metallization structures include diffused copper atoms.Interfaces between the first and second barrier metals and the first andsecond gold metallization structures, respectively, are substantiallydevoid of metallic copper.

Those skilled in the art will recognize additional features andadvantages upon reading the following detailed description, and uponviewing the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The elements of the drawings are not necessarily to scale relative toeach other. Like reference numerals designate corresponding similarparts. The features of the various illustrated embodiments can becombined unless they exclude each other. Embodiments are depicted in thedrawings and are detailed in the description which follows.

FIG. 1 depicts a semiconductor substrate with a device formed in thesubstrate and having first and second exposed terminals, according to anembodiment.

FIG. 2 depicts the formation of a barrier layer on the substrate and theformation of a seed layer on the barrier layer, according to anembodiment.

FIG. 3 depicts masking the substrate with a mask having first and secondopenings that are laterally aligned with the first and second terminalsof the semiconductor device, according to an embodiment.

FIG. 4 depicts electroplating the device with a gold electrolytesolution such that first and second gold metallization structures formin the first and second openings on the seed layer, according to anembodiment.

FIG. 5 depicts removing the mask, according to an embodiment.

FIG. 6 depicts removing portions of the seed layer and the barrier layerso as to electrically isolate the first and second gold metallizationstructures, according to an embodiment.

FIG. 7 depicts diffusing the remaining portions of the seed layer intothe first and second gold metallization structures to form interfacesbetween the barrier layer and the first and second gold metallizationstructures that are substantially devoid of the seed layer in itsmetallic state, according to an embodiment.

FIG. 8 depicts an alternate process sequence in which the diffusion stepis performed prior to removing portions of the seed layer and thebarrier layer such that gold from the first and second goldmetallization structures laterally diffuses into the seed layer,according to an embodiment.

FIG. 9 depicts removing the portions of the seed layer and the barrierlayer from the device in FIG. 8 selective to gold, according to anembodiment.

DETAILED DESCRIPTION

Embodiments disclosed herein include a method of forming a goldmetallization structure, such as a power line or interconnect line thatis electrically connected to one or more semiconductor devices. The goldmetallization structure is formed by an electroplating using aphotolithography mask to define the geometry of the metallization lines.The seed layer is formed from a noble metal other than gold, such ascopper. After the electroplating process, portions of the seed layer areremoved, e.g., by etching. The remaining metallic portion of the seedlayer underneath the gold metallization structure is diffused into thegold structure. As a result, the device is substantially devoid of theseed layer in its metallic state.

Advantageously, the embodiments disclosed herein provide anelectroplated gold metallization line that is resistant toelectromigration and/or diffusion, while using a seed layer materialother than gold (e.g., copper) that is easily and reliably etched away.Although gold seed layers may be used to form an electroplated goldmetallization line, a drawback of this technique is that the removal ofthe seed layer (e.g., by etching with aqua regia) often leads toredeposition of metallic gold. This presents a high risk of electricalshort. An alternative to electroplating is an evaporation andresist-lift-off technique. However, minimum structure widths anddistances required for modem semiconductor device metallizations e.g.,below 30 μm) may be difficult or impossible to achieve usingresist-lift-off techniques.

By using copper as a seed layer, most of the copper material can beeasily removed from the device, e.g., by wet-chemical etch techniques,with a low likelihood of redeposition. The remaining copper in thedevice can be diffused into the gold structures. As a result, the goldstructures include diffused copper atoms, but there is little to nometallic state bulk copper that is at risk of corrosion, oxidation orelectromigration. That is, the processes described herein utilizecopper, as a seed layer, but the copper is rendered inert by a diffusionstep. Further, by using an electroplating process with a copper seedlayer, the embodiments described herein can be easily andcost-effectively implemented into existing copper electroplating processtechnologies, e.g., by selecting the appropriate electrolyte solution.

Referring to FIG. 1, a semiconductor substrate 100 is depicted. Thesemiconductor substrate 100 may be formed from any commonly knownsemiconductor material, such as silicon (Si), silicon carbide (SiC),germanium (Ge), a silicon germanium crystal (SiGe), gallium nitride(GaN), gallium arsenide (GaAs), and the like. The semiconductorsubstrate 100 may be a bulk substrate or alternatively may include oneor more epitaxially grown layers 102.

One or more semiconductor devices are formed in the substrate 100. Thesemiconductor devices may be any device requiring electrical connection.Examples of such semiconductor devices MOSFETs, IGBTs, diodes, etc.Terminals of the semiconductor devices are exposed from the substrate.That is, the semiconductor substrate 100 of FIG. 1 is formed with atleast one semiconductor device that is ready for electrical connectionto a metallization layer. This may be done according to knowntechniques. The terminal may be an input terminal or output terminal ofthe device, such as a source region, a drain region, a gate electrode,an emitter region, a collector region, etc. The terminal may be a regionof semiconductor material or an electrical conductor formed in thesubstrate.

According to an embodiment, the substrate 100 includes a powertransistor (e.g., an IGBT) with first and second terminals 104, 106 thatare source and drain regions of the power transistor. According to anembodiment, contract trenches 110 extend from the main surface 108 ofthe substrate 100 to first and second terminals 104, 106 so as to exposethe first and second terminals 104, 106. The first and second terminals104, 106 are laterally separated from one another. As used herein, alateral direction refers to a direction that is parallel to a mainsurface 108 of the semiconductor substrate 100.

Referring to FIG. 2, a barrier layer 112 is formed on the substrate 100.The barrier layer 112 is formed from an electrically conductive materialthat is configured to prevent electromigration of an adjoining metalconductor (e.g., copper). For example, the barrier layer 112 may beformed from tantalum (Ta), tantalum-nitride (TaN), titanium (Ti),titanium-nitride (TiN), titanium-tungsten (TiW), and the like. Accordingto an embodiment, the barrier layer 112 is between 0.01-1 μm thick. Thebarrier layer 112 may be formed by a deposition technique (e.g.,sputtering, evaporation-or chemical vapor deposition), for example.

The barrier layer 112 is formed along the surface 108 of the substrate100 and covers at least one of the first and second terminals 104, 106.As shown in FIG. 2, the barrier layer 112 covers both the first andsecond terminals 104, 106. According to an embodiment, a continuousbarrier layer 112 portion contacts both the first and second terminals104, 106 and extends along the surface 108 of the substrate 100 betweenthe first and second terminals 104, 106. Alternatively, one or moreintervening conductive layers (not shown) may be provided between thebarrier layer 112 and the terminals 104, 106. Further, other barrierlayers (not shown) may be formed on the substrate 100, either above orbelow the depicted barrier layer 112. The barrier layer 112 may be acomplete layer that is formed along the entire surface of the substrate100 or alternatively may cover only a portion of the substrate 100 thatincludes at least one of the terminals 104, 106.

Also referring to FIG. 2, a seed layer 114 is formed on the barrierlayer 112. The seed layer 114 extends over at least one of the first andsecond terminals 104, 106, and may be coextensive with the barrier layer112. That is, the seed layer 114 may have the same lateral boundaries asthe barrier layer 112, and may completely cover the substrate 100.According to an embodiment, a continuous seed layer 114 portion coversthe continuous barrier layer 112 portion. Thus, the continuous seedlayer 114 portion is arranged over and extends between the first andsecond terminals 104, 106. Further, in embodiments that include thecontact trenches 110, the continuous portions of the seed layer 114 andthe barrier layer 112 may extend into these contact trenches.

The seed layer 114 may be formed from any electrical conductor that issuitable as cathode electrode for an electroplating process. Examples ofsuch conductors include noble metals other than gold such as silver(Ag), platinum (Pt) or palladium (Pd) and copper (Cu). As used herein,the term noble metal refers to a metal that is resistant to chemicalaction, does not corrode, and is not easily dissolved by acid (e.g.,acids associated with an electroplating process). According to anembodiment, the seed layer 114 is a layer of copper (Cu). The seed layer114 may have a thickness of between 0.1-3 μm. The seed layer 114 may beformed by a deposition technique (e.g., sputtering, evaporation orchemical vapor deposition), for example.

Referring to FIG. 3, the substrate 100 including the seed layer 114 andthe barrier layer 112 is masked. According to an embodiment, aphotoresist mask 116 having first and second openings 118, 120 is formedon the substrate 100. The photoresist mask 116 may be formed accordingto commonly known techniques. The first and second openings 118, 120 arelaterally aligned with the first and second terminals 104, 106,respectively As shown in FIG. 3, the mask 116 is configured such thatunmasked portions of the seed layer 114 and the barrier layer 112, whichextend over the first and second terminals 104, 106, are exposed by thefirst and second openings 118, 120, respectively. Likewise, maskedportions of the seed layer 114 are covered by the mask 116. In the eventthat the substrate 100 includes contact trenches 110, the unmaskedportions of the seed layer 114 and barrier layer 112 are arranged in thecontact trenches 110.

The mask 116 may be patterned in any desired geometry. For example, ifthe substrate 100 includes a plurality of devices, the mask 116 may bepattered with openings corresponding to the input and/or outputterminals of each device. Furthermore, the minimum geometric features ofthe photoresist mask 116 (e.g., minimum widths and pitch) may beadjusted, depending upon the configuration of the devices and theapplication requirements.

Referring to FIG. 4, an electroplating process is performed. As usedherein, electroplating refers to an electrodeposition technique in whichthe device is submerged in an electrolyte solution and a DC circuit sformed with the device. The DC circuit includes an anode and a cathodeplaced in an electrolyte solution. Under a DC bias, dissolved metalcations in the electrolyte solution deposit on the cathode. As a result,an essentially pure metal structure develops on the seed cathode.

In the electroplating process of the presently disclosed embodiment, agold electrolyte solution 120, such as a cyanidic or sulfidic solution,is used. An anode 122 is placed in the gold electrolyte solution 120 andthe seed layer 114 is used as a cathode of the DC circuit. As a result,essentially pure gold is electrodeposited on the seed layer 114. Theanode 122 may be formed from any conductive material that is resistantto corrosion (e.g., platinum). The thickness of the gold that isdeposited on the seed layer 114 depends upon parameters of theelectroplating process such as duration, concentration of cations in theelectrolyte solution, current flow and geometric parameters, such asopen area and arrangement of the semiconductor devices.

In the embodiment of FIG. 4, the unmasked portions of the seed layer 114are electroplated to form first and second gold metallization structures124, 126 arranged in the first and second mask openings 118, 120,respectively. Thus, the geometry of the photoresist mask 116 defines thegeometry of gold metallization structures 124, 126. As shown in FIG. 5,the mask 116 is subsequently removed from the substrate 100.

Referring to FIG. 6, the (previously) masked portions of the seed layer114 and the barrier layer 112 are removed. According to an embodiment,etching techniques are utilized to remove material from the seed layer114 and the barrier layer 112 and consequently remove the (previously)masked portions of the seed layer 114 and the barrier layer 112. Forexample, both the seed layer 114 and the barrier layer 112 may be etchedby a wet chemical etching process. Alternatively, the barrier layer 112may be etched by a plasma etching process. The etching of the seed layer114 and the barrier layer 112 is selective to gold so that the first andsecond gold metallization structures 124, 126 remain substantiallyintact after etching. In the embodiment of FIG. 6, lateral sections ofthe seed layer 114 and the barrier layer 112 between the first andsecond gold metallization structures 124, 126 are completely etched awayso that the first and second gold metallization structures 124, 126 areelectrically isolated from one another. In other words, there is noconductive path between the first and second gold metallizationstructures 124, 126 through the seed layer 114 or barrier layer 112.

According to an embodiment, the etching process is performed such thatportions of the of the seed layer 114 underneath the first and secondgold metallization structures 124, 126 are also etched away. In otherwords, etching of the seed layer 114 and the barrier layer 112 includesetching both the unmasked portions and part of the masked portions. Thisunder-etch at the foundation of the first and second gold metallizationstructures 124, 126 may be a consequence of etching the seed layer 114for a sufficient duration to ensure that all of the seed layer 114material between the first and second gold metallization structures 124,126 is removed, and that the first and second gold metallization strum124, 126 are electrically isolated from one another.

Referring to FIG. 7, the remaining unmasked portions of the seed layer114 are diffused into the first and second gold metallization structures124, 126. As a result, the metallic state portions of the seed layer 114are effectively eradicated. For example, in the event that the seedlayer 114 is formed from copper, copper atoms disperse into the goldmetallization structures 124, 126. Further, metallic state copperbetween the gold metallization structures 124, 126 and the barrier layer112 is diminished.

According to an embodiment, diffusing the noble metal from the unmaskedportion of the seed layer 114 includes diffusing all of the noble metalbetween the barrier layer 112 and the gold metallization structures 124,126 into the gold metallization structures 124, 126 to form an interfacebetween the barrier layer 112 and the metallization at structures 124,126 that is substantially devoid of the noble metal in its metallicstate. In other words, the diffusion process is controlled so that thegold of the first and second gold metallization structures 124, 126directly contacts the barrier layer 112. In the embodiments in which theseed layer 114 is formed from copper, this may be achieved by annealingthe substrate 100 with the gold metallization structures 124, 126 andthe metallic state copper of the seed layer 114 at a temperature between200° and 400° C. for a duration of 10 to 60 minutes so that the coppercompletely diffuses in to the gold metallization structures 124, 126.

In the above described methods, the first and second gold metallizationstructures 124, 126 are electrically connected to the first and secondterminals 104, 106, respectively, via the barrier layer 112. That is, afirst region of the barrier layer 112 arranged between the first goldmetallization structure 124 and the first terminal 104 provides anelectrically conductive path. Likewise, a second region of the barrierlayer 112 arranged between the second gold metallization structure 126and the second terminal 106 provides an electrically conductive path.This electrical connection between the terminals 104, 106 and the goldmetallization structures 124, 126 is not necessarily exclusively to thebarrier layer 112, and may be completed through other regions and/orconductive materials

In the above depicted sequence, diffusing the noble metal of the seedlayer 114 is performed after removing the masked portions of the seedlayer 114 and the barrier layer 112. As previously explained, all of thematerial of the seed layer 114 may be removed except for the portions ofthe seed layer 114 arranged underneath the gold metallization structures124, 126. Subsequently, all of the remaining seed layer 114 material(e.g., copper) may be diffused into the gold metallization structures124, 126 by the diffusion process. In other words, the device may besubstantially free of the seed layer 114 material in its metallic stateafter the diffusion process.

By diffusing the all of the metallic state copper (in the embodimentsthat utilize copper as the seed layer 114 material) into the goldmetallization structures 124, 126 the resulting semiconductor deviceincludes a high-performance metallization that is susceptible toelectrical short due to the effects of electromigration, diffusion,and/or oxidation. The diffusion technique produces gold metallizationstructures 124, 126 with a percentage of copper. Depending upon thetemperature and time conditions of the diffusion process, the copper maybe concentrated towards the bottom of the structures 124, 126. However,this copper is in the form of diffused copper atoms (i.e., dispersedatoms) and not in the metallic state. Further, the interfaces betweenthe first and second terminals 104, 106 and the first and second goldmetallization structures 124, 126, respectively, can be formed to besubstantially devoid of metallic copper. In other words, the methods anddevices described herein avoid the drawbacks associated with copper, byenveloping the copper from the seed layer 114 into the goldmetallization structures 124, 126.

By utilizing a patterned electrodeposition technique, advantageousstructure widths are possible in the presently disclosed methods.According to an embodiment, a width (W) of the first and second goldmetallization structures 124, 126 is less than 10 μm and a separationdistance (D) between the first and second gold metallization structures124, 126 is less than 10 μm. A variety of different dimensions arepossible, and the minimum spacing between the metallization structuresis determined by the capabilities of the photolithography process.

The device of FIG. 7 may be subsequently processed according to commonlyknown techniques. For example, a dielectric layer (not shown) thatelectrically insulates the first and second gold metallizationstructures 124, 126 from one another may be formed on the substrate 100.Higher level metallization layers may be formed on the substrate 100 aswell.

FIGS. 8-9 depict an alternate embodiment in which the diffusing thenoble metal of the seed layer 114 is performed prior to removing themasked portions of the seed layer 114 and the barrier layer 112. In thisembodiment, the device may be formed according to the process stepsdisclosed with reference to FIGS. 1-5. Subsequently, a diffusion processsuch as the process described with reference to FIG. 7 is performed. Ifthe seed layer 114 is formed from copper, the substrate 100 includingthe seed layer 114 and the first and second gold metallizationstructures 124, 126 may be annealed at temperature between 200° and 400°C. so that all of the metallic state copper underneath the first andsecond gold metallization structures 124, 126 diffuses away from theinterface. Concurrently, gold material from the first and second goldmetallization structures 124, 126 laterally diffuses into the maskedportions of the seed layer 114. FIG. 8 depicts an exemplary boundary ofthe laterally diffused gold. According to an embodiment, the golddiffuses into the seed layer 114 to a certain lateral distance,depending on temperature and diffusion duration. For example, the goldmay be laterally diffused into the seed layer by a distance of 0.3-0.5μm.

As shown in FIG. 9, the masked portions of the seed layer 114 and thebarrier layer 112 are subsequently removed, The seed layer 114 may beremoved by a wet chemical etch and the barrier layer 112 may be removedby a wet chemical etch or a plasma etch, for example. One advantage ofthe process sequence of FIGS. 8-9 is increased mechanical stability ofthe metallization structures 124, 126. This increased mechanicalstability arises due to the laterally diffused gold, which expands thefoundation of the metallization structures 124, 126.

The term “substantially” encompasses absolute conformity with arequirement as well as minor deviation from absolute conformity with therequirement due to manufacturing process variations, assembly, and otherfactors that may cause a deviation from the ideal. Provided that thedeviation is within process tolerances so as to achieve practicalconformity, the term “substantially” encompasses any of thesedeviations. For example, a “substantially” pure metal may include a verylow percentage of alloy metal atoms, but nonetheless provides thedesired qualities (e.g., electrical resistance, resistance to corrosion,etc.) of a pure metal in a semiconductor device. Likewise, an interfacethat is substantially devoid of the noble metal in its metallic statemay have a small percentage of noble metal in the metallic state, solong as this amount is within acceptable process tolerances and the riskof electrical short attributable to the metallic state noble metal isnegligible or non-existent.

Within this specification the terms “in electrical contact,”“electrically connected,” “in low resistive electric contact,”“electrically coupled,” “in low ohmic contact,” and “in low resistiveelectric connection” are used synonymously. Likewise, the terms “inresistive electric contact,” “in ohmic contact,” and “in resistiveelectric connection” are used synonymously within this specification.

Spatially relative terms such as “under,” “below,” “lower,” “over,”“upper,” “above,” “beneath” and the like, are used for ease ofdescription to explain the positioning of one element relative to asecond element. These terms are intended to encompass differentorientations of the device in addition to different orientations thanthose depicted in the figures. Further, terms such as “first,” “second,”and the like, are also used to describe various elements, regions,sections, etc. and are also not intended to be limiting. Like termsrefer to like elements throughout the description.

As used herein, the terms “having,” “containing,” “including,”“comprising” and the like are open-ended terms that indicate thepresence of stated elements or features, but do not preclude additionalelements or features. The articles “a,” “an” and “the” are intended toinclude the plural as well as the singular, unless the context clearlyindicates otherwise.

It is to be understood that the features of the various embodimentsdescribed herein may be combined with each other, unless specificallynoted otherwise.

Although specific embodiments have been illustrated and describedherein, it will be appreciated by those of ordinary skill in the artthat a variety of alternate and/or equivalent implementations may besubstituted for the specific embodiments shown and described withoutdeparting from the scope of the present invention. This application isintended to cover any adaptations or variations of the specificembodiments discussed herein. Therefore, it is intended that thisinvention be limited only by the claims and the equivalents thereof.

What is claimed is:
 1. A semiconductor device, comprising: asemiconductor substrate comprising first and second terminals of one ormore semiconductor devices; first and second barrier metal regionselectrically connected to the first and second terminals, respectively;and first and second gold metallization structures electricallyconnected to the first and second terminals via the first and secondbarrier metal regions, respectively; wherein the first and second goldmetallization structures comprise diffused copper atoms, and whereininterfaces between the first and second barrier metals and the first andsecond gold metallization structures, respectively, are substantiallydevoid of metallic copper.
 2. The semiconductor device of claim 1,wherein a width of the first and second gold metallization structures isless than 10 μm, and wherein a separation distance between the first andsecond gold metallization lines is less than 10 μm.
 3. The semiconductordevice of claim 1, wherein the first terminal is a source terminal of atransistor, wherein the second terminal is a drain terminal of thetransistor, and wherein the first and second gold metallizationstructures are electrically insulated from one another.